Integration of a MIM capacitor with a plate formed in a well region and with a high-k dielectric

ABSTRACT

A MIM capacitor is formed on a semiconductor substrate having a top surface and including regions formed in the surface selected from a Shallow Trench Isolation (STI) region and a doped well having exterior surfaces coplanar with the semiconductor substrate. A capacitor lower plate is either a lower electrode formed on the STI region in the semiconductor substrate or a lower electrode formed by a doped well formed in the top surface of the semiconductor substrate that may have a silicide surface. A capacitor HiK dielectric layer is formed on or above the lower plate. A capacitor second plate is formed on the HiK dielectric layer above the capacitor lower plate. A dual capacitor structure with a top plate may be formed above the second plate with vias connected to the lower plate protected from the second plate by sidewall spacers.

BACKGROUND OF THE INVENTION

This invention relates to a method for making a capacitor structure for high-density integrated circuits and the structure produced thereby, and more particularly relates to a method for making a Metal-Insulator-Metal (MIM) capacitor having a High K (HiK) dielectric constant and the structure produced thereby.

In the semiconductor industry, currently there is a tread towards the use of metal gates for CMOS and HiK dielectric materials in high-density integrated circuit devices. This trend is based on the need to employ metal gates to reduce the problem of high leakage currents that result from device scaling to smaller and smaller dimensions as TOX (Thickness Of Silicon Oxide ) is reduced as the silicon oxide is thinned down for constant field sealing.

In industry, MIM capacitors are used in integrated circuits, especially those integrated circuits used in Radio Frequency (RF) and other high-frequency applications. The requirement for high capacitance density/lower foot print capacitors which are compatible with ever high frequency applications has driven the industry to use HiK dielectric materials for the insulator in the MIM capacitor.

FIGS. 1A-1C are schematic sectional drawings show in three steps in the prior art process of forming a MIM capacitor 10.

In FIG. 1A, the basic layers used to form the MIM capacitor 10 are shown on the top of the BEOL structure 12. First a bottom electrode 14 is formed over the BEOL structure 12 followed by formation of a MIM dielectric (MD) layer 16. The MD layer 16 is then covered by a top electrode layer 18 which in turn is covered by an etch stop layer 20. A resist mask 22 is formed over the etch stop layer 20.

FIG. 1B shows the structure 10 of FIG. 1A after the step of etching away those portions of the etch stop layer 20 and the top electrode layer 18 aside from the mask 22 by anisotropic etching down to the MD layer 16. Below the mask 22, the etch stop layer 20 has been shaped into a narrowed etch stop layer 20E and the top electrode layer 18 has been etched to form a top electrode 18E, with both narrowed etch stop layer 20E and the top electrode layer 18 being aligned with the resist mask 22.

FIG. 1C shows the structure 10 of FIG. 1B after removal of mask 22 followed by etching of a hole extending down through the narrowed etch stop layer 20E to the top surface of the top electrode layer 18 and after etching a pair of holes through the MD layer 16 down to the top surface of the bottom electrode 14. A conductive via 25 has been formed extending down through the narrowed etch stop layer 20E to the top surface of the top electrode 18E. In addition, a dielectric layer 19 has been deposited on the structure 10. Then two conductive vias 27 have been formed reaching down through the dielectric layer 19 and the MD layer 16 to the top surface of the bottom electrode 14 on either side of the top electrode 18E. The conductive via 25 connects to the top electrode of the BEOL MIM capacitor 10 to wire 26. The conductive vias 27 connect the bottom electrode 14 of the BEOL MIM to wire 28.

Heretofore MIM structures have been integrated into the Back End Of the Line (BEOL) structures of integrated circuit devices. However we have observed that it will eventually be impossible to integrate MIM structures into BEOL structures as the heights of Vias are reduced to smaller and smaller dimensions. Accordingly it is an object of this invention to find an alternative solution which avoids integration of MIM structures into BEOL structures.

SUMMARY OF THE INVENTION

The introduction of metal gates and HiK dielectric materials creates a demand for advanced passive device integration schemes, which will be needed in the future to complement advanced CMOS. The integration scheme of the present invention eliminates the need for BEOL MIM integration, which will as stated above will eventually be impossible due to the reduction of Via heights. With the integration scheme of the present invention that issue is overcome.

The present invention is an integration scheme, which uses metal gates and a HiK dielectric layer as components of MIM capacitors.

In accordance with this invention, the bottom plate of a MIM capacitor is composed of silicided polysilicon or silicon (Si) followed by deposition of a HiK dielectric layer and top plate in post silicide processing.

The main idea uses a metal gate and HiK dielectric to make a MIM capacitor as part of the CMOS integration.

A first advantage of use of a metal gate and HiK dielectric to make a MIM capacitor includes provision of a capacitor compatible with metal/HiK gate CMOS integration. A second advantage is that the MIM capacitor produced has better linearity as compared to the current MOS capacitors and hence a better RF device is produced. Thirdly, the use of the HiK dielectric layer in the MIM capacitors provides high capacitance density which is suitable for both decoupling and RF capacitors. In addition, there is no need for BEOL MIM integration, which is increasingly difficult with each new generation of integrated circuit devices because of the requirement of reduction of the via height.

The invention and objects and features thereof will be more readily apparent from the following detailed description and appended claims when taken with the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A-1C are schematic sectional drawings show in three steps in the prior art process of forming a MIM capacitor.

FIGS. 2A-2F are schematic sectional views which show a semiconductor device in an early stage of manufacturing in preparation for formation of the seven embodiments of this invention shown in FIGS. 3A, 4A, 5A, 6A, 7A, 8A and 9A.

FIG. 3A is schematic sectional view of a semiconductor device in accordance with a first embodiment of this invention.

FIG. 3B is a flow chart of the process of manufacturing of the semiconductor device of FIG. 3A in accordance with the method of this invention.

FIG. 4A is schematic sectional view of a semiconductor device in accordance with a second embodiment this invention.

FIG. 4B is a flow chart of the process of manufacturing of the semiconductor device of FIG. 4A in accordance with the method of this invention.

FIG. 5A is schematic sectional view of a semiconductor device in accordance with a third embodiment of this invention.

FIG. 5B is a flow chart of the process of manufacturing of the semiconductor device of FIG. 5A in accordance with the method of this invention.

FIG. 6A is schematic sectional view of a semiconductor device in accordance with a fourth embodiment this invention.

FIG. 6B is a flow chart of the process of manufacturing of the semiconductor device of FIG. 6A in accordance with the method of this invention.

FIG. 7A is schematic sectional view of a semiconductor device in accordance with a fifth embodiment of this invention.

FIG. 7B is a flow chart of the process of manufacturing of the semiconductor device of FIG. 7A in accordance with the method of this invention.

FIG. 8A is schematic sectional view of a semiconductor device in accordance with a sixth embodiment this invention.

FIG. 8B is a flow chart of the process of manufacturing of the semiconductor device of FIG. 8A in accordance with the method of this invention.

FIG. 9A is schematic sectional view of a semiconductor device in accordance with a seventh embodiment of this invention.

FIG. 9B is a flow chart of the process of manufacturing of the semiconductor device of FIG. 9A in accordance with the method of this invention.

Several embodiments of this invention are explained and described below with reference to the accompanying drawings.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Processing Steps to Form Ancillary Structures for Preferred Embodiments

FIGS. 2A-2F are schematic sectional views which show a semiconductor device 30 in an early stage of manufacturing thereof in preparation for formation of the seven embodiments of this invention shown in FIGS. 3A, 4A, 5A, 6A, 7A, 8A and 9A.

FIG. 2A shows the semiconductor device 30 comprising a P-doped semiconductor substrate 31 in an initial stage of manufacturing in step 70 in the flow charts of FIGS. 3B, 4B, 5B, 6B, 7B, 8B, and 9B. Semiconductor substrate 31 has a planar top surface 31T and a bottom surface 31B.

FIG. 2B shows the semiconductor device 30 of FIG. 2A after formation of a patterned mask layer 32 on the planar to surface 31T. The patterned mask layer 32 has a window 32W extending therethrough down to expose a portion of the left side of the top surface 31T of the P-doped semiconductor substrate 31 in step 71 in the flow charts of FIGS. 3B, 4B, 5B, 6B, 7B, 8B, and 9B. The window 32W in the mask layer 32 has substantially vertical sidewalls 32S extending from the top to the bottom of the mask layer 32.

FIGS. 2C-2D show the semiconductor device 30 of FIG. 2B illustrating the processing step performed in step 72 in the flow charts of FIGS. 3B, 4B, 5B, 6B, 7B, 8B, and 9B.

In FIG. 2C, a shallow trench 31 TR is shown having substantially vertical sidewalls 31S etched into P-doped semiconductor substrate 31 by etching through the window 32W through the resist mask layer 32 down through the top surface 31T of the P-doped semiconductor substrate 31. Preferably a space remains between the foot 31F of the trench TR and the bottom 31B of the semiconductor substrate 31. In FIG. 2C the sidewalls 31S of the trench TR are shown aligned with the sidewalls 32S of the window 32W in the mask layer 32.

FIG. 2D shows the semiconductor device 30 of FIG. 2C after the resist mask layer 32 was stripped and a Shallow Trench Isolation (STI) region 33 was formed by deposition of silicon dioxide filling the trench TR. The STI region 33 has been planarized to the level of the top surface of silicon substrate 31 leaving the top surface 33T of the STI region 33 in substantially the same plane as the top surface 31T of the semiconductor substrate 31.

FIG. 2E shows the semiconductor device 30 of FIG. 2D after the process steps 73 and 74 of FIG. 3B of forming a second mask layer 34 patterned as a well implant mask, formed over the semiconductor device 30. The second mask layer 34 includes a window 34W with sidewalls 34S extending through the second mask layer 34 down to the top surface of a portion of the right side of the P-doped semiconductor substrate 31. FIG. 2E shows the ion implantation of ions 35T through the window 34W, thereby forming a P-doped well or N-doped well 35 in the P-substrate 31. The well 35 has a floor 35F spaced above the bottom 31B of the semiconductor substrate 31. The doped well 35 is aligned with the window 34W in the mask 34. FIG. 2E illustrates the processing performed in steps 73 end 74 in the flow charts of FIGS. 3B, 4B, 5B, 6B, 7B, 8B, and 9B.

FIG. 2F shows the semiconductor device 30 of FIG. 2E after removing the second mask layer 34, leaving the semiconductor device with the STI region 33 on the left and the doped well 35 on the right. There are several different structures comprising embodiments of this invention which can be formed over either the STI region 33 or the doped well 35 which are described below. FIG. 2F illustrates the processing performed in step 75 in the flow charts of FIGS. 3B, 4B, 5B, 6B, 7B, 8B, and 9B.

First Embodiment

FIG. 3A is schematic sectional view of a semiconductor device 301 including a Metal Insulator-Metal (MIM) capacitor 310 in accordance with this invention. The semiconductor device 301 is manufactured according to the process of this invention, as shown by the flow chart of FIG. 3B.

The Metal Insulator-Metal (MIM) capacitor 310 is formed on a base comprising a semiconductor substrate 31 having a top surface 31T. A Shallow Trench Isolation (STI) region 33 is formed in the region of the surface 31T of the substrate 31. The STI region 33 has a top surface 33T coplanar with the top surface 31T of the semiconductor substrate 31. The MIM capacitor lower plate 38M is a metal electrode formed on the top surface 33T of the STI region 33. A HiK dielectric layer 40 of the MIM capacitor 310 is formed on the top surface 38T of the lower plate 38M of the MIM capacitor 310. The MIM capacitor top plate 42M is formed on the HiK dielectric layer 40 above the lower plate 38M. An etch stop layer 44 is formed above the top plate electrode 42M.

The semiconductor device 301 of FIG. 3A is formed on the STI portion of the semiconductor device 30 of FIG. 2F after completion of manufacturing steps of FIG. 3B performed on the STI region 33 of the P-doped semiconductor substrate 31 manufactured in accordance with the steps 76A-86 shown in the flow chart of FIG. 3B.

FIG. 3B shows the sequence of manufacturing the semiconductor device 301 of FIG. 3A including at least the process steps 70, 71 and 72 shown in FIGS. 2A-2E. The semiconductor device 301 is formed on the top surface 33T of the STI region 33 (with or without the N doped or P doped well region 35 formed in steps 73, 74 and 75 of FIG. 3B.)

As indicated above, the semiconductor device 301 has been formed over the top surface 33T of the STI region 33 in the semiconductor substrate 31 of FIG. 2E. Deposition step 76A has been performed resulting in the formation of a blanket metal layer 38M covering the top surface 33T of the STI region 33 of the device 301 and the top surface 31T of the STI region 33. The metal layer 38M comprises a gate electrode layer, e.g. a polysilicon doped gate electrode layer or a metal layer which is to be formed into the lower plate of the MIM capacitor 310.

In step 77A of FIG. 3B, the metal (gate) lower electrode 38M is patterned to lie well within the borders of the STI region 33 (on the top surface 33T thereof) leaving a margin thereabout so that the electrode 38M does not contact the top surface 31T or any other part of the silicon substrate 31 aside from the STI region 33. In other words, the sidewalls 38S of the electrode 38M are spaced away from the exposed top surface 31T of the silicon substrate 31. The processing can be the conventional process for forming Metal gates of MOSFET devices, as is well understood by those skilled in the art.

In step 78 of FIG. 3B, sidewall spacers 39 composed of a dielectric material such as silicon dioxide (SiO₂) are formed on the sidewalls 38S of the metal (gate) lower electrode 38M.

In step 79A of FIG. 3B, a blanket HiK dielectric layer 40 composed of a High-K dielectric material, i.e. Ta₂O₅, BaTiO₃, HfO₂, ZrO₂ or Al₂O₃, is deposited on the top surface 38T of the patterned metal (gate) lower electrode layer 38M, the spacers 39 and the exposed portions of the top surface 33T of the STI region 33 and the silicon substrate 31T to form the High-K dielectric 40 for the MIM capacitor 310 which is being formed. Then a patterning mask (not shown) is formed over the blanket HiK dielectric layer 40 and the unwanted portions of HiK dielectric layer 40 are removed re-exposing the portions of the top surface 33T of the STI region 33 and the top surface 31T of the silicon substrate 31 which had been exposed after step 78.

In step 80, FIG. 3B a blanket MIM top electrode layer 42M of the MIM capacitor 310 is deposited on the semiconductor device 301. The layer 42M covers the exposed surfaces of the device 301 at that stage in the process of formation thereof. The top electrode layer 42M may be composed of a material selected from the group consisting of TiN, Ti, Ta, TaN, and W or a combination thereof in all embodiments.

In step 81A of FIG. 3B, deposit a blanket silicon nitride (Si₃N₄) etch stop layer 44 on the top surface of the blanket MIM top electrode layer 42M.

In step 82A of FIG. 3B, form a patterning mask (not shown) and pattern the Si₃N₄ etch stop layer 44 and the MIM top electrode layer 42, etching down therethrough stopping at the top surface 40T of the HiK dielectric layer 40, the exterior surfaces of the sidewall spacers 39, the top surface 33T of the STI region 33 and the top surface 31T of the silicon substrate 31. The patterning mask of step 82A was designed so narrow the etch stop layer 44 and the MIM top electrode 42 with sidewalls 42S so that they are narrower than the stack comprising the HiK dielectric layer 40 and the metal lower electrode 38M. In that way room remains for formation of electrical contacts from above extending through the HiK dielectric layer 40 to the metal gate electrode 38M.

Then in accordance with the conventional step 83A in FIG. 3B, form shallow via holes 53 and deep via holes 54 extending down through the silicon nitride (Si₃N₄) etch stop layer 44 and the HiK dielectric layer 40 by patterning the blanket dielectric layer 49, the silicon nitride (Si₃N₄) etch stop layer 44 and the HiK dielectric layer 40. The via holes 53 and 54 are formed by first forming a blanket deposit of a dielectric layer 49 composed of a material such as BSPG (not shown for convenience of illustration.) Then a via mask is formed and deep via holes 54 are formed extending through the blanket dielectric layer 49 and through the lateral portion of HiK dielectric layer 40 aside from MIM top electrode 42M 54 located between sidewalls 38S and 42S extending down to the top surface 38T of the metal (gate) lower electrode 38M. In addition the shallow via holes 53 formed between the sidewalls 38S of the MIM top electrode 42M extend through layer 49 and etch stop layer 44 down into contact with the top surface 42T of the MIM top electrode 42M.

Then in accordance with the conventional via formation step 84 in FIG. 3B, a short pair of vias 47S are formed in the shallower set of via holes 53 extending down to the top surface 42T of the electrode layer 42M. A long set of vias 45L are formed in the deep set of via holes 54 extending down to the top surface of the metal lower electrode 38M.

In step 85, M1 metallization element is formed above the vias 45L/47S. Metallization elements 48 and 46 are formed over short vias 47S and long vias 45L respectively.

Finally, step 86 ends the process shown by FIG. 3B.

Second Embodiment

FIG. 4A is schematic sectional view of a semiconductor device 401 in accordance with this invention including a Metal Insulator-Metal (MIM) capacitor 410. The semiconductor device 401 is manufactured in accordance with the process of this invention which is shown by the flow chart of FIG. 4B.

As shown in FIG. 4A the MIM capacitor 410 is formed on a base comprising a semiconductor substrate 31 having a top surface 31T with an STI region 33 formed in a region of the surface 31T of the substrate 31. Moreover, also as in FIG. 3A the STI region 33 has a top surface 33T coplanar with the top surface 31T of the semiconductor substrate 31. In the case of FIG. 4A, however, the MIM capacitor 410 has a silicided lower plate 38L. A portion 38P of the silicided lower plate 38L is a conductive (doped) polysilicon layer 38P formed on the top surface 33T of the STI region 33. The complementary portion of the laminated lower plate 38L is a conventional conductive (doped) silicide layer 38C (formed in step 184 in FIG. 4B) in the top surface of the polysilicon layer 38P, as will be well understood by those skilled in the art. A capacitor HiK dielectric layer 40 is formed on the top surface 38V of the silicide layer 38C of the MIM capacitor lower plate 38M. The top plate 42M of the MIM capacitor is formed on the top surface 40T of the HiK dielectric layer 40 above the MIM capacitor laminated lower plate 38L. An etch stop layer 44 is formed above the top plate electrode 42M.

In detail, FIG. 4A shows a semiconductor device 401 which is a portion of the semiconductor device 30 of FIG. 2F in a later stage of manufacturing comprising a P-doped semiconductor substrate 401 manufactured in accordance with the steps 76B-86 shown in the flow chart of FIG. 4B. FIG. 4B shows the sequence for manufacturing the semiconductor device 401 including at least the process steps 70, 71 and 72 shown in FIGS. 2A-2E. The semiconductor device 401 is formed on the top surface 33T of the STI region 33 (with or without the N doped or P doped well region 35 formed in steps 73, 74 and 75 of FIG. 4B.)

As indicated above, the semiconductor device 401 has been formed over the top surface 33T of the STI region 33 in the semiconductor substrate 31 of FIG. 2E. In deposition step 76B, a blanket polysilicon layer 38P is deposited covering the top surfaces 33T of the STI region 33 and the surface 31T of the substrate 31 of device 401. The polysilicon layer 38P may comprise a gate electrode layer, e.g. a polysilicon doped gate electrode layer.

In step 77B of FIG. 4B, the blanket polysilicon layer 38P of the lower plate 38L (i.e. blanket polysilicon layer 38P and silicide layer 38C) has been patterned by masking and etching to lie well within the borders of the STI region 33 (on the top surface 33T thereof) leaving a margin thereabout so that patterned lower plate 38L does not contact the top surface 31T or any other part of the silicon substrate 31 aside from the STI region 33. In other words, the sidewalls 38S of the polysilicon layer 38P of the lower plate 38L are spaced away from the exposed top surface 31T of the silicon substrate 31. The processing can be the conventional process for forming Metal gates of MOSFET devices, as will be well understood by those skilled in the art.

In step 78 of FIG. 4B, sidewall spacers 39 composed of a dielectric material such as silicon dioxide (SiO₂) are formed on the sidewalls 38S of the lower plate 38L.

In step 184 of FIG. 4B, a silicidation process is performed forming a silicide layer 38C in the upper surface of the polysilicon layer 38P creating the lower plate 38L with sidewalls 38S and sidewall spacers 39 extending to the top of the silicide layer 38C as shown in FIG. 4A.

In step 79A of FIG. 4B, a blanket HiK dielectric layer 40 composed of a High-K dielectric material, i.e. Ta₂O₅, BaTiO₃, HfO₂, ZrO₂ or Al₂O₃, is deposited on the top surface 38V of the sillicide layer 38C the spacers 39 and the exposed portions of the top surface 33T of the STI region 33 and the top surface 31T of the silicon substrate 31 to prepare for formation of the High-K dielectric of the MIM capacitor 410. Then a patterning mask (not shown) is formed over the blanket HiK dielectric layer 40 and the unwanted portions of HiK dielectric layer 40 are removed re-exposing the portions of the top surface 33T of the STI region 33 and the top surface 31T of the silicon substrate 31 which were exposed after step 78 leaving a patterned HiK dielectric layer 40 for the MIM capacitor 410.

In step 80, FIG. 4B a blanket MIM top electrode layer 42M of the MIM capacitor 410 is deposited on the semiconductor device 301 covering the exposed surfaces thereof at that stage in the process of formation thereof.

In step 81A of FIG. 4B, a blanket silicon nitride (Si₃N₄) etch stop layer 44 is deposited on the top surface of the blanket MIM top electrode layer 42M.

In step 82A of FIG. 4B, form a patterning mask (not shown) and pattern the Si₃N₄ etch stop layer 44 and the MIM top electrode layer 42, etching down therethrough stopping at the top surface 40T of the HiK dielectric layer 40, the exterior surfaces of the sidewall spacers 39, the top surface 33T of the STI region 33 and the top surface 31T of the silicon substrate 31. The patterning mask of step 82A was designed so that the etch stop layer 44 and the MIM top electrode 42 with sidewalls 42S are narrower than the stack comprising the HiK dielectric layer 40 and the metal lower electrode 38M. In that way room remains for formation of electrical contacts from above extending through the HiK dielectric layer 40 to the top surface 38V of the silicide layer 38C.

Then in accordance with the conventional step 83A in FIG. 4B, form shallow via holes 53 and deep via holes 54 extending down through the silicon nitride (Si₃N₄) etch stop layer 44 and through the HiK dielectric layer 40 by patterning the blanket dielectric layer 49, the silicon nitride (Si₃N₄) etch stop layer 44 and the HiK dielectric layer 40. The via holes 53 and 54 are formed by first forming a blanket deposit of a dielectric layer 49 composed of a material such as BSPG (not shown for convenience of illustration.) Then a via mask is formed and the deep via holes 54 are formed extending through the blanket dielectric layer 49 and through the lateral portion of HiK dielectric layer 40 aside from MIM top electrode 42M located between sidewalls 38S and 42S extending down to the top surface 42T of the silicide layer 38C. In addition the shallow via holes 53 are formed between the sidewalls 38S of the MIM top electrode 42M extending through layer 49 and etch stop layer 44 into contact with the top surface 42T of the MIM top electrode 42M.

Then in accordance with the conventional via formation step 84 in FIG. 4B, a short pair of vias 47S are formed in the shallower set of via holes 53 extending down to the top surface 42T of the MIM top electrode 42M. A long set of vias 45L are formed in the deep set of via holes 54 extending down to the top surface of the silicide layer 38C.

In step 85, M1 metallization elements 46/48 are formed above the vias 45L/47S.

Step 86 ends the process shown by FIG. 4B.

Third Embodiment

FIG. 5A is schematic sectional view of a semiconductor device 501 including a Metal Insulator-Metal (MIM) capacitor 510 in accordance with this invention. The semiconductor device 501 is manufactured according to the process of this invention shown by the flow chart of FIG. 5B.

As shown in FIG. 5A the MIM capacitor 510 is formed on a base comprising a semiconductor substrate 31 having a top surface 31T. A P/N (Positively or Negatively ) doped well 35 is formed in a region of the surface 31T of the substrate 31. The P/N doped well 35, which serves as the lower plate of the MIM capacitor 510, has a top surface 35T coplanar with the top surface 3IT of the P/N doped well 35 in the semiconductor substrate 31. A capacitor HiK dielectric layer 160 is formed on the top surface 35T of the doped P/N well 35. The top plate 142 of the MIM capacitor 510 is formed on the top surface 160T of the HiK dielectric layer 160 above the doped P/N well 35, i.e. the lower plate of the MIM capacitor 510. Sidewall spacers 139 composed of a dielectric material such as silicon dioxide (SiO₂) are formed covering the sidewalls 142S of the top plate electrode 142 b and on sidewalls of said HiK dielectric layer 160. A silicon nitride (Si₃N₄) etch stop layer 144 is formed above the top plate electrode 142. A blanket BPSG dielectric layer 149 covers the device 501 A set of shallow via holes 53 located between the sidewalls 142S of the MIM top plate electrode 142 extend down through the blanket dielectric layer 149 and the silicon nitride (Si_(3N) ₄) etch stop layer 144 to the top surface 142T of the MIM top plate electrode 142. The etch stop layer 144, the capacitor HiK dielectric layer 160, and the top plate 142 of the MIM capacitor 510 are narrower than the P/N well 35 leaving space for both sidewall spacers 139 and a set of tall, vertical vias 145T formed in an extra deep set of via holes 57 so that the vertical vias 145T extend down into electrical and mechanical contact with the top surface of a set of silicide contact pads 141A that have been formed in the top surface 35T of the P/N well 35, aside from the capacitor HiK dielectric layer 160, and the top plate 142 of the MIM capacitor 510.

In detail, FIG. 5A shows a semiconductor device 401 which is a portion of the semiconductor device 30 of FIG. 2F in a later stage of manufacturing comprising a P-doped semiconductor substrate 501 manufactured in accordance with the steps 79B-86 shown in the flow chart of FIG. 5B, which shows the sequence for manufacturing the semiconductor device 501 including at least the process step 73-75 shown in FIGS. 2A-2E. Semiconductor device 501 is formed on the top surface 35T of the doped P/N well 35 (with or without the STI region 33 formed in steps 71-72 in FIG. 5B.)

As indicated above, the semiconductor device 501 has been formed in and above the P/N well 35 in the semiconductor substrate 31 of FIG. 2E and above the top surface 35T thereof.

In step 79B of FIG. 5B, a blanket HiK dielectric layer 160 composed of a High-K dielectric material, i.e. Ta₂O₅, BaTiO₃, HfO₂, ZrO₂ or Al₂O₃, is deposited on the top surface 35T of the doped P/N well 35 and the top surface 31T of the silicon substrate 31 to prepare for formation of the High-K dielectric of the MIM capacitor 510. Then a patterning mask (not shown) is formed over the blanket HiK dielectric layer 160 and the unwanted portions of HiK dielectric layer 160 are removed re-exposing the portions of the top surface 33T of the STI region 33 and the top surface 31T of the silicon substrate 31 which were exposed after step 78 leaving a patterned HiK dielectric layer 160 for the MIM capacitor 510.

In deposition step 76C, of FIG. 5B, a blanket conductive electrode layer 142 has been formed covering the dielectric layer 160 and every other exposed surface of the device in preparation for formation of the top plate electrode 142.

In step 77C of FIG. 5B the blanket conductive electrode layer 142 has been patterned by masking and etching to lie well within the borders of the P/N well 35 (above the top surface 35T thereof and above the dielectric layer 160) leaving a margin thereabout so that patterned top plate 142 does not contact the top surface 31T or any other part of the silicon substrate 31 or top surface 35T of the P/N well 35. In other words, the sidewalls 142S of the polysilicon layer 142 of the top plate 142 are spaced away from the exposed top surface 31T of the silicon substrate 31 and the top surface 35T of the P/N well 35. The processing can be the conventional process for forming Metal gates of MOSFET devices, as will be well understood by those skilled in the art.

In step 78B of FIG. 5B, sidewall spacers 139 composed of a dielectric material such as silicon dioxide (SiO₂) are formed covering the sidewalls 142S of the top plate electrode 142.

In step 81B of FIG. 5B, a blanket silicon nitride (Si₃N₄) etch stop layer 144 is deposited on the top surface of the blanket MIM top electrode layer 142 and patterned to be aligned with the top plate electrode 142, leaving at least a portion of the periphery of the top surface 35T of the P/N well 35 and the top surface 31T of the substrate 31 exposed.

In step 284 of FIG. 5B, a silicidation process is performed to create one or more silicide contact pads 141A in the top surface 35T of the P/N well 35 extending from the spacers 139 across the previously exposed top surface 35T of the P/N well 35 to the top surface 31T of the substrate 31.

Then in a conventional step 83B in FIG. 5B, after a blanket dielectric layer 149 was formed over the device 501, a set of shallow via holes 53 is formed extending down through the silicon nitride (Si₃N₄) etch stop layer 144 by patterning the blanket dielectric layer 149 and the silicon nitride (Si₃N₄) etch stop layer 144. Extra deep via holes 57 are formed reaching down to the silicide contact pads 141A. The via holes 53 and 54 are formed by first forming the blanket deposit of the dielectric layer 149 composed of a material such as BSPG (not shown for convenience of illustration.) Then a via mask is formed and the extra deep via holes 57 are formed extending through the blanket dielectric layer 149 extending down to the top surface of the silicide layer 141A. In addition the shallow via holes 53 are formed between the sidewalls 142S of the MIM top plate electrode 142 extending through layer 149 and etch stop layer 144 into contact with the top surface 142T of the MIM top plate electrode 142.

Then in accordance with the conventional via formation step 84 in FIG. 5B, a short pair of vias 147L are formed in the shallower set of via holes 53 extending down to the top surface 142T of the MIM top plate electrode 142. A tall set of vias 145T are formed in the deep set of via holes 57 extending down to the top surface of the silicide layer 141A.

Finally in step 85, M1 metallization elements 146/148 are formed above the vias 145T/147L.

Step 86 ends the process shown by FIG. 5B.

Fourth Embodiment

FIG. 6A is schematic sectional view of a semiconductor device 601 including a MIM capacitor 610 in accordance with this invention. The semiconductor device 601 is manufactured in accordance with the process of this invention shown by the flow chart of FIG. 6B.

In the embodiment of FIG. 6A, a lower plate 150 of the MIM capacitor 610 comprises the combination of the doped well 35 with a silicide layer 141B formed in the entire top surface of the P/N well 35. A HiK dielectric layer 160 is formed on the top surface of the silicide layer 141B above doped well 35 and silicide layer 141B. The top plate electrode 142 of the MIM capacitor 610 is formed on the top surface 160T of the HiK dielectric layer 160. The top plate 142 of the dual MIM capacitor 610 is formed with sidewalls 142S well inside of the location of the periphery of the silicide layer 141B and the P/N well 35.

As shown in FIG. 6A the MIM capacitor 610 is formed on a base comprising a semiconductor substrate 31 having a top surface 31T. A P/N well 35 is formed in a region of the surface 31T of the substrate 31. As in FIG. 5A, the P/N well 35 originally had a top surface coplanar with the top surface 31T of the semiconductor substrate 31, but a suicide layer 141B has been formed across the entire top surface of the P/N well 35 producing a recessed top surface 35T′ of the P/N well 35. As stated above, the combination of the P/N well 35 and the silicide layer 141B form the lower plate 150 of the MIM capacitor 610, and the capacitor HiK dielectric layer 160 is formed on the top surface 141T of the silicide layer 141B. The top plate electrode 142 of the MIM capacitor 510 is formed on the top surface 160T of the HiK dielectric layer 160 above the silicide layer 141B and the doped P/N well 35, i.e. the lower plate 150 of the MIM capacitor 610. An etch stop layer 144 is formed above the top surface 142T of the top plate electrode 142.

In detail, FIG. 6A shows a semiconductor device 601 which is a portion of the semiconductor device 30 of FIG. 2F in a later stage of manufacturing comprising a P-doped semiconductor substrate 601 manufactured in accordance with the steps from step 176 to step 86 shown in the flow chart of FIG. 6B, which shows the sequence of preliminary steps performed to manufacture the semiconductor device 601 including at least the process steps from step 73 to step 75 shown in FIGS. 2A-2E and FIG. 3. The semiconductor device 601 is formed in and on the doped P/N well 35 (with or without the STI region 33 formed in steps 71-72 in FIG. 5B.)

As indicated above, the semiconductor device 601 has been formed in part within the P/N well 35 in the semiconductor substrate 31 of FIG. 2E and in part above the top surface thereof.

In step 176 of FIG. 6B, a silicidation process is performed forming a silicide layer 141B in the upper surface of the P/N well 35 of FIG. 6A completing the formation of the lower plate 150 of the MIM capacitor 610.

In step 79C of FIG. 6B, a blanket HiK dielectric layer 160 composed of a High-K dielectric material, i.e. Ta₂O₅, BaTiO₃, HfO₂, ZrO₂ or Al₂O₃, is deposited on the top surface 141T of the sillicide layer 141B (above doped P/N well 35) and on the top surface 31T of the silicon substrate 31 to prepare for formation of the High-K dielectric of the MIM capacitor 610.

In deposition step 76C, of FIG. 6B, a blanket conductive electrode layer 142 has been formed covering the top surface 160T of the dielectric layer 160 and every other exposed surface of the device in preparation for formation of the top plate electrode 142. The processing can be the conventional process for forming Metal gates of MOSFET devices, as will be well understood by those skilled in the art.

In step 81C of FIG. 6B, a blanket silicon nitride (Si₃N₄) etch stop layer 144 is deposited on the top surface of the blanket MIM top electrode layer 142.

In step 77C a patterning mask (not shown) is formed over the blanket silicon nitride (Si₃N₄) etch stop layer 144, the blanket conductive electrode layer 142, and the HiK dielectric layer 160. Then the peripheral portions of etch stop layer 144, the blanket conductive electrode layer 142, and the HiK dielectric layer 160 are removed by etching to re-expose the peripheral portions of the top surface 141T of the silicide layer 141B and the top surface 31T of the silicon substrate 31 leaving a patterned top plate electrode 142 and a patterned HiK dielectric layer 160 for the MIM capacitor 610 with sufficient surface area on the top surface 141T of the periphery of the silicide layer 141B exposed for contact with vias 145T. The etching of the layers 144, 142, and 160 forms sidewalls 142S aligned as those in FIG. 5A. In other words, the sidewalls 142S of the polysilicon layer 142 of the top plate 142 are spaced laterally (recessed) away from the exposed top surface 31T of the silicon substrate 31.

Then in a conventional step 83B in FIG. 6B, after a blanket dielectric layer 149 was formed over the device 501, a set of shallow via holes 53 is formed extending down through the silicon nitride (Si₃N₄) etch stop layer 144 by patterning the blanket dielectric layer 149 and the silicon nitride (Si₃N₄) etch stop layer 144. Extra deep via holes 57 are formed reaching down to the suicide layer 141B. The via holes 53 and 57 are formed by first depositing the blanket dielectric layer 149 composed of a material such as BSPG (not shown for convenience of illustration.) Then a via mask is formed and the extra deep via holes 57 are formed extending through the dielectric layer 149 extending down to the top surface of the silicide layer 141B. In addition the shallow via holes 53 are formed between the sidewalls 142S of the MIM top plate electrode 142 extending through dielectric layer 149 and etch stop layer 144 into contact with the top surface 142T of the MIM top plate electrode 142.

Then in accordance with the conventional via formation step 84 in FIG. 6B, a short pair of vias 147L are formed in the shallower set of via holes 53 extending down to the top surface 142T of the MIM top plate electrode 142. A tall set of vias 145T are formed in the deep set of via holes 57 extending down to the top surface of the silicide layer 141B.

Then in step 85 of FIG. 6B, M1 metallization elements 146/148 are formed above the vias 145T/147L.

Finally, step 86 ends the process shown by FIG. 6B.

Fifth Embodiment

FIG. 7A is schematic sectional view of a semiconductor device 701 including a dual MIM capacitor 710 in accordance with this invention. The semiconductor device 701 is manufactured in accordance with the process of this invention shown by the flow chart of FIG. 7B.

As shown in FIG. 7A the dual MIM capacitor 710 is formed in and on a base of the semiconductor substrate 31 which has a top surface 31T. As with FIG. 5A, a P/N well 35 is formed in a region of the surface 31T of the substrate 31, with the P/N well 35 serving as the entire lower plate of the dual MIM capacitor 710. The P/N well 35 has a top surface 35T coplanar with the top surface 31T of the semiconductor substrate 31. A first HiK dielectric layer 160 is formed on the top surface 35T of the P/N well 35. A middle electrode 138M formed of metal (e.g. the gate electrode layer of the device) is formed directly upon the top surface of the first HiK dielectric layer 160. A second HiK dielectric layer 140C is formed on the top surface 138T of the middle electrode 138M. The top plate electrode 242 is formed on the top surface 140T of the second HiK dielectric layer 140 above the doped P/N well 35, i.e. the lower plate 35. An etch stop layer 244 is formed above the top plate electrode 242. The lower plate 35 of the MIM capacitor 710 is electrically connected to the top plate 242 of the MIM capacitor. Thus, dual MIM-metal/HiK gate integration is provided.

In detail, FIG. 7A shows a semiconductor device 701 which is a portion of the semiconductor device 30 of FIG. 2F in a later stage of manufacturing comprising a P-doped semiconductor substrate 701 manufactured according to the steps 76D-86 shown in the flow chart of FIG. 7B, which shows the sequence of preliminary steps performed to manufacture the semiconductor device 701 including at least the process step 73-75 shown in FIGS. 2A-2E. Semiconductor device 701 is formed in and on the doped P/N well 35 (with or without the STI region 33 formed in steps 71-72 in FIG. 5B.)

As indicated above, the semiconductor device 701 has been formed in and above the P/N well 35 in the semiconductor substrate 31 of FIG. 2E and above the top surface thereof.

In step 79D of FIG. 7B, a blanket first High-K dielectric layer 160 which is composed of a High-K dielectric material, i.e. Ta₂O₅, BaTiO₃, HfO₂, ZrO₂ or Al₂O₃, is deposited on the top surface 35T of the doped P/N well 35 and on the top surface 31T of the substrate 31 to prepare for patterning of the High-K dielectric layer 160 of the MIM capacitor 710.

In deposition step 76D, of FIG. 7B, a blanket conductive metal (gate) middle electrode 138M is deposited covering the top surface 160T of the first High-K dielectric layer 160 and every other exposed surface of the device in preparation for formation of the metal middle electrode 138M. The processing can be the conventional process for forming Metal gates of MOSFET devices, as will be well understood by those skilled in the art.

In step 79E of FIG. 7B, a blanket second High-K dielectric layer 140 having a top surface 140T is deposited covering the top surface 138T of the middle electrode 138M and the remainder of the exposed surfaces of device 701.

In step 77D a middle electrode stack mask (not shown) is formed over the top surface 140T of the second High-K dielectric layer 140 for patterning all of the second High-K dielectric layer 140, the conductive metal (gate) middle electrode 138M and first High-K dielectric layer 160 followed by etching. The etching of the layers 140, 138M, and 160 forms a middle electrode stack with sidewalls 138S aligned as those in FIG. 5A. In other words, the sidewalls 138S of the middle electrode stack are spaced laterally (recessed) away from the exposed top surface 31T of the silicon substrate 31. Then the middle electrode stack mask is removed.

In step 78B of FIG. 7B, sidewall spacers 139 composed of a dielectric material such as silicon dioxide (SiO₂) are formed covering the sidewalls 138S of the top plate electrode 138 and the first High-K dielectric layer 160.

In step 80, of FIG. 7B, a blanket conductive top electrode layer 242 has been deposited covering the top surface 140T second High-K dielectric layer 140C and every other exposed surface of the device in preparation for formation of the top plate electrode 242.

In step 81D of FIG. 7B, a blanket silicon nitride (Si₃N₄) etch stop layer 244 with a top surface 244T is deposited on the top surface 242T of the blanket MIM top electrode layer 242.

In step 82A in FIG. 7B a second patterning mask (not shown) is formed over the blanket silicon nitride (Si₃N₄) etch stop layer 244, the blanket conductive electrode layer 242. Then the peripheral portions of the etch stop layer 244 and the blanket conductive electrode layer 242 are removed by etching to re-expose the peripheral portions of the top surface 140T of second High-K dielectric layer 140C and the top surface 35T of the well 35 and the top surface 31T of the silicon substrate 31 leaving a patterned structure 253 comprising the top plate electrode 242 and a patterned etch stop layer 244 for the MIM capacitor 710 with sufficient surface area on the top surface 140T of the periphery of the second High-K dielectric layer 140C exposed for contact with a via 147L. The etching of the layers 244 and 242 forms sidewalls 242S having an alignment recessed inside of the vertical planes of sidewalls 138S of the middle electrode 138M. In other words, the sidewalls 242S of the polysilicon layer 242 of the top plate electrode 242 are spaced away from the exposed top surface 140T of the periphery of the second High-K dielectric layer 140C.

In step 284 in FIG. 7B silicide contacts 141A are formed on top of exposed portions of the P/N well 35 aside from the spacers 139, as in FIGS. 5A/5B.

Then in a conventional step 83C in FIG. 7B, after a blanket dielectric layer 149 was formed over the device 501, a shallow via hole 56 is formed extending down to the top surface 242T of the top electrode 242 through the silicon nitride (Si₃N₄) etch stop layer 244 by patterning the blanket dielectric layer 149 and the silicon nitride (Si₃N₄) etch stop layer 244. A deeper via hole 55 is formed reaching down through the dielectric layer 149 and the second High-K dielectric layer 140C to the top surface 138T of the middle electrode 138M. Two extra deep via holes 57 are formed reaching down to the silicide contacts 141A. The via holes 55, 56, and 57 are formed by first forming the blanket deposit of the dielectric layer 149 composed of a material such as BSPG (not shown for convenience of illustration.) Then a via mask is formed and the extra deep via holes 57 are formed extending through the blanket dielectric layer 149 extending down to the top surface of the silicide contacts 141A. The shallow via hole 56 is formed between the sidewalls 242S of the MIM top plate electrode 242 extending to the top surface 242T of the top electrode 242 through layer 149 and etch stop layer 244 into contact with the top surface 242T of the MIM top plate electrode 242. The via hole 55 is formed between the sidewalls 138S of the MIM middle electrode 138M extending through layer 149 and layer 140 into contact with the top surface 138T of the middle electrode 138M.

Then in accordance with the conventional via formation step 84 in FIG. 7B, a short via 147S is formed in the shallow via hole 56 extending down to the top surface 242T of the MIM top plate electrode 242. A tall set of vias 145T are formed in the deep set of via holes 57 extending down to the top surface of the silicide layer 141A. A long via 147L is formed in the via hole 55 extending down to the top surface 138T of the middle electrode 138M.

Finally in step 85 of FIG. 7B, M1 metallization element 146A is formed above the leftmost of the vias 145T, M1 metallization element 148 is formed above the long via 147L, and M1 metallization element 146B is formed above the short via 147S and the rightmost one of the tall vias 145T.

Step 86 ends the process shown by FIG. 7B.

Sixth Embodiment

FIG. 8A is schematic sectional view of a semiconductor device 801 including a dual MIM capacitor 810 in accordance with this invention. The semiconductor device 801 is manufactured in accordance with the process of this invention shown by the flow chart of FIG. 8B.

As shown in FIG. 8A the dual MIM capacitor 810 is formed in and on a base of the semiconductor substrate 31 with a top surface 31T. As with FIG. 5A, a P/N well 35 is formed in a region of the surface 31T of the substrate 31, with the P/N well 35 serving as the entire lower plate of the dual MIM capacitor 810. The P/N well 35 has a top surface 35T coplanar with the top surface 31T of the semiconductor substrate 31. A first HiK dielectric layer 160 is formed on the top surface 35T of the P/N well 35. A polysilicon middle electrode layer 138P capped with a silicide middle electrode layer 138C is formed directly upon the top surface 160T of the first HiK dielectric layer 160. A second HiK dielectric layer 140C is formed on the top surface 138T of the silicide middle electrode layer 138C. The top plate electrode 242 is formed on the top surface 140T of the second HiK dielectric layer 140 above the doped P/N well 35, i.e. the lower plate 35. An etch stop layer 244 is formed above the top plate electrode 242. The lower plate 35 of the MIM capacitor 810 is electrically connected to the top plate 242 of the MIM capacitor 810. Thus, dual MIM-metal/HiK gate integration is provided.

In detail, FIG. 8A shows a semiconductor device 801 which is a portion of the semiconductor device 30 of FIG. 2F in a later stage of manufacturing comprising a P-doped semiconductor substrate 801 manufactured according to the steps 79D-86 shown in the flow chart of FIG. 8B, which shows the sequence of preliminary steps performed to manufacture the semiconductor device 801 including at least the process steps from step 73 to step 75 shown in FIGS. 2A-2E and FIG. 3. Semiconductor device 801 is formed in and on the doped P/N well 35 (with or without the STI region 33 formed in steps 71-72 in FIG. 5B.)

As indicated above, the semiconductor device 801 has been formed in and above the P/N well 35 in the semiconductor substrate 31 of FIG. 2E and above the top surface thereof.

In step 79D of FIG. 8B, a blanket first High-K dielectric layer 160 with a top surface 160T, which is composed of a High-K dielectric material, i.e. Ta₂O₅, BaTiO₃, HfO₂, ZrO₂ or Al₂O₃, is deposited on the top surface 35T of the doped P/N well 35 and on the top surface 31T of the 31 to prepare for patterning of the High-K dielectric layer 160 of the MIM capacitor 810.

In deposition step 76E, of FIG. 8B, a blanket polysilicon middle electrode layer 138P is deposited covering the top surface 160T of the first High-K dielectric layer 160 and every other exposed surface of the device in preparation for formation of the middle electrode 138P/138C. The processing can be the conventional process for forming Metal gates of MOSFET devices, as will be well understood by those skilled in the art.

In step 77E a middle electrode stack mask (not shown) is formed over the top surface 138T of the polysilicon middle electrode layer 138P for patterning both of the layer 138P and first High-K dielectric layer 160 followed by etching. The etching of the layers 138P and 160 forms a middle electrode stack 138P/160 with sidewalls 138S aligned as those in FIG. 5A. In other words, the sidewalls 138S of the middle electrode stack 138P/160 are spaced laterally (recessed) away from the exposed top surface 31T of the silicon substrate 31. Then the mask used to pattern the middle electrode stack is removed.

In step 78B of FIG. 8B, sidewall spacers 139 composed of a dielectric material such as silicon dioxide (SiO₂) are formed covering the sidewalls 138S of the middle electrode 138P and the first High-K dielectric layer 160.

In step 484 of FIG. 8B, a silicidation process is performed forming a silicide layer 138B in the upper surface of the polysilicon middle electrode layer 138P of FIG. 8A completing the formation of the middle electrode plate 138P of the MIM capacitor 810.

In step 79F of FIG. 8B, a blanket second High-K dielectric layer 140C having a top surface 140T is deposited covering the top surface 138T of the middle electrode 138C/138P and the remainder of the exposed surfaces of device 801.

In step 80, of FIG. 8B, a blanket conductive top electrode layer 242 has been deposited covering the top surface 140T of the second High-K dielectric layer 140C and every other exposed surface of the device in preparation for formation of the top plate electrode 242.

In step 81E of FIG. 8B, a blanket silicon nitride (Si₃N₄) etch stop layer 244 with a top surface 244T is deposited on the top surface of the blanket MIM top electrode layer 242.

In step 82B in FIG. 8B a second patterning mask (not shown) is formed over the blanket silicon nitride (Si₃N₄) etch stop layer 244 and the blanket conductive electrode layer 242. Then the peripheral portions of the etch stop layer 244 and the blanket conductive electrode layer 242 are removed by etching to re-expose the peripheral portions of the top surface 140T of second High-K dielectric layer 140C and the top surface 35T of the well 35 and the top surface 31T of the silicon substrate 31 leaving a patterned structure 253 comprising the top plate electrode 242 and a patterned etch stop layer 244 for the MIM capacitor 810 with sufficient surface area on the top surface 140T of the periphery of the second High-K dielectric layer 140C exposed for contact with a via 147L. The etching of the layers 244 and 242 forms sidewalls 242S having an alignment recessed inside of the vertical planes of sidewalls 138S of the middle electrode 138C/138P. In other words, the sidewalls 242S of the polysilicon layer 242 of the top plate electrode 242 are spaced away from the exposed top surface 140T on the periphery of the second High-K dielectric layer 140C.

In step 284 in FIG. 8B silicide contacts 141A are formed on top of exposed portions of the P/N well 35 aside from the spacers 139 as in FIGS. 5A/5B and 7A/7B.

Then in a conventional step 83C in FIG. 8B, after a blanket dielectric layer 149 was formed over the device 501, a shallow via hole 56 extending to the top surface 242T of the top electrode 242 is formed extending down through the silicon nitride (Si₃N₄) etch stop layer 144 by patterning the blanket dielectric layer 149 and the silicon nitride (Si₃N₄) etch stop layer 244. A deeper via hole 55 is formed reaching down through the dielectric layer 149 and the second High-K dielectric layer 140C to the top surface 138T of the middle electrode 138C/138P. Two extra deep via holes 57 are formed reaching down to the silicide contacts 141A. The via holes 55, 56, and 57 are formed by first forming the blanket deposit of the dielectric layer 149 composed of a material such as BSPG (not shown for convenience of illustration.) Then a via mask is formed and the extra deep via holes 57 are formed extending through the blanket dielectric layer 149 extending down to the top surface of the silicide contacts 141A. The shallow via hole 56 is formed between the sidewalls 242S of the MIM top plate electrode 242 extending through layer 149 and etch stop layer 244 into contact with the top surface 242T of the MIM top plate electrode 242. The via hole 55 is formed between the sidewalls 138S of the MIM middle electrode 138C/138P extending through layer 149 and layer 140 into contact with the top surface 138T of the middle electrode 138C/138P.

Then in accordance with the conventional via formation step 84 in FIG. 8B, a short via 147S is formed in the shallow via hole 56 extending down to the top surface 242T of the MIM top plate electrode 242. A tall set of vias 145T are formed in the deep set of via holes 57 extending down to the top surface of the silicide layer 141A. A long via 147L is formed in the via hole 55 extending down to the top surface 138T of the middle electrode 138C/138P.

Finally in step 85 of FIG. 8B, M1 metallization element 146A is formed above the leftmost one of the vias 145T, M1 metallization element 148 is formed above the long via 147L, and M1 metallization element 146B is formed above the short via 147S and the rightmost one of the tall vias 145T.

Step 86 ends the process shown by FIG. 8B.

Seventh Embodiment

FIG. 9A is schematic sectional view of a semiconductor device 901 including a dual MIM capacitor 910 in accordance with this invention. The semiconductor device 901 is manufactured in accordance with the process of this invention shown by the flow chart of FIG. 9B.

Referring to FIG. 9A, the MIM capacitor 910 includes a P/N doped well 35 formed in a region of the surface 31T of the substrate 31, with the doped P/N well 35 capped with a silicide layer 141B extending across the entire top surface of the P/N well 35 serving as the lower plate 150 of the MIM capacitor 910. The silicide layer 141B has a top surface 35T′ coplanar with the top surface 31T of the semiconductor substrate 31 with the top surface 35T′ of the P/N well 35 spaced therebelow. A capacitor HiK dielectric layer 160 is formed on the top surface 141T of the silicide layer 141B. The top plate 242 of the MIM capacitor 910 is formed across the top surface 160T of the HiK dielectric layer 160 above silicide layer 141B and the doped P/N well 35, i.e. the lower plate 150 of the MIM capacitor 910. An etch stop layer 244 is formed above the top plate electrode 242, A HiK dielectric layer 160 is formed on the top surface of the silicide layer 141B above doped well 35 and silicide layer 141B. The top plate electrode 242 of the MIM capacitor 610 is formed on the top surface 160T of the HiK dielectric layer 160. The top plate 142 of the dual MIM capacitor 610 is formed with sidewalls 142S well inside of the location of the periphery of the silicide layer 141B and the P/N well 35.

As shown in FIG. 9A the MIM capacitor 910 is formed on a base comprising a semiconductor substrate 31 having a top surface 31T. The P/N well 35 is formed in a region of the surface 31T of the substrate 31. As in FIG. 6A, the P/N well 35 originally had a top surface coplanar with the top surface 31T of the semiconductor substrate 31, but a silicide layer 141B has been formed extending across the entire top surface of the P/N well 35 producing a recessed top surface 35T′ of the P/N well 35. As stated above, the combination of the P/N well 35 and the silicide layer 141B form the lower plate 150 of the dual MIM capacitor 910, and the capacitor HiK dielectric layer 160 is formed on the top surface 141T of the silicide layer 141B. The metal (gate) middle electrode 138M of the MIM capacitor 910 is formed on the top surface 160T of the HiK dielectric layer 160 above the silicide layer 141B and the doped P/N well 35, i.e. the lower plate 150 of the MIM capacitor 610. A second HiK dielectric layer 140C is formed on the top surface 138T of the middle electrode layer 138M. The top plate electrode 242 is formed on the top surface 140T of the second HiK dielectric layer 140 above the doped P/N well 35 of the lower plate 150. An etch stop layer 244 is formed above the top plate electrode 242. The lower plate 35 of the MIM capacitor 910 is electrically connected to the top plate 242 of the MIM capacitor 910. Thus, dual MIM-metal/HiK gate integration is provided.

In detail, FIG. 9A shows a semiconductor device 901 which is a portion of the semiconductor device 30 of FIG. 2F in a later stage of manufacturing thereof, comprising a P-doped semiconductor substrate 901 manufactured according to the steps from step 176 to step 86 shown in the flow chart of FIG. 9B, which shows the sequence of preliminary steps performed to manufacture the semiconductor device 901 including at least the process steps from step 73 to step 75 shown in FIGS. 2A-2E. Semiconductor device 901 is formed in and on the doped P/N well 35 (with or without the STI region 33 formed in steps 71-72 in FIG. 5B.)

As indicated above, the semiconductor device 901 has been formed in and above the P/N well 35 in the semiconductor substrate 31 of FIG. 2E and above the top surface thereof.

In step 176 of FIG. 9B, a silicidation process is performed forming a silicide layer 141B in the upper surface of the P/N well 35 of FIG. 9A completing the formation of the lower plate 150 of the MIM capacitor 910.

In step 79D of FIG. 9B, a blanket first High-K dielectric layer 160 with a top surface 160T, that is composed of a High-K dielectric material, i.e. Ta₂O₅, BaTiO₃, HfO₂, ZrO₂ or Al₂O₃, is deposited on the top surface 141T of the silicide layer 141B and on the top surface 31T of the substrate 31 to prepare for patterning the High-K dielectric layer 160 of the MIM capacitor 910.

In deposition step 76B, of FIG. 9B, a blanket polysilicon middle electrode layer 138P is deposited covering the top surface 160T of the first High-K dielectric layer 160 and every other exposed surface of the device in preparation for formation of the middle electrode 138M. The processing can be the conventional process for forming Metal gates of MOSFET devices, as will be well understood by those skilled in the art.

In step 77 a middle electrode stack mask (not shown) is formed over the top surface 138T of the polysilicon middle electrode layer 138P for patterning both of the layer 138P and first High-K dielectric layer 160 followed by etching. The etching of the layers 138P and 160 forms a middle electrode stack 138M/160 with sidewalls 138S aligned as those in FIG. 5A. In other words, the sidewalls 138S of the middle electrode stack 138M/160 are spaced laterally (recessed) away from the exposed top surface 31T of the silicon substrate 31. Then the mask used to pattern the middle electrode stack is removed.

In step 79E of FIG. 9B, a blanket second High-K dielectric layer 140C having a top surface 140T is deposited covering the top surface 138T of the middle electrode 138M and the remainder of the exposed surfaces of device 901.

In step 80, of FIG. 9B, a blanket conductive top electrode layer 242 has been deposited covering the top surface 140T of the second High-K dielectric layer 140C and every other exposed surface of the device in preparation for formation of the top plate electrode 242.

In step 81F of FIG. 9B, a blanket silicon nitride (Si₃N₄) etch stop layer 244 with a top surface 244T is deposited on the top surface of the blanket MIM top electrode layer 242.

In step 82B in FIG. 9B a second patterning mask (not shown) is formed over the blanket silicon nitride (Si₃N₄) etch stop layer 244 and the blanket conductive electrode layer 242. Then the peripheral portions of the etch stop layer 244 and the blanket conductive electrode layer 242 are removed by etching to re-expose the peripheral portions of the top surface 140T of second High-K dielectric layer 140C and the top surface 35T of the well 35 and the top surface 31T of the silicon substrate 31 leaving a patterned structure 253 comprising the top plate electrode 242 and a patterned etch stop layer 244 for the MIM capacitor 910 with sufficient surface area on the top surface 140T of the periphery of the second High-K dielectric layer 140C exposed for contact with a via 147L. The etching of the layers 244 and 242 forms sidewalls 242S recessed inside of the vertical planes of sidewalls 138S of the middle electrode 138M. In other words, the sidewalls 242S of the polysilicon layer 242 of the top plate electrode 242 are spaced away from the exposed top surface 140T on the periphery of the second High-K dielectric layer 140C.

Then in a conventional step 83C in FIG. 9B, after a blanket dielectric layer 149 was formed over the device 501, a shallow via hole 56 extending to the top surface 242T of the top electrode 242 is formed extending down through the silicon nitride (Si₃N₄) etch stop layer 144 to the top surface 242T of the top electrode 242 by patterning the blanket dielectric layer 149 and the silicon nitride (Si₃N₄) etch stop layer 244. A deeper via hole 55 is formed reaching down through the dielectric layer 149 and the second High-K dielectric layer 140C to the top surface 138T of the middle electrode 138M. Two extra deep via holes 57 are formed reaching down to the silicide contacts 141A. The via holes 55, 56, and 57 are formed by first forming the blanket deposit of the dielectric layer 149 composed of a material such as BSPG (not shown for convenience of illustration.) Then a via mask is formed and the extra deep via holes 57 are formed extending through the blanket dielectric layer 149 extending down to the top surface of the silicide contacts 141A. The shallow via hole 56 is formed between the sidewalls 242S of the MIM top plate electrode 242 extending through layer 149 and etch stop layer 244 into contact with the top surface 242T of the MIM top plate electrode 242. The via hole 55 is formed between the sidewalls 138S of the MIM middle electrode 138M extending through layer 149 and layer 140 into contact with the top surface 138T of the middle electrode 138M.

Then in accordance with the conventional via formation step 84 in FIG. 9B, a short via 147S is formed in the shallow via hole 56 extending down to the top surface 242T of the MIM top plate electrode 242. A tall set of vias 145T are formed in the deep set of via holes 57 extending down to the top surface of the silicide layer 141B. A long via 147L is formed in the via hole 55 extending down to the top surface 138T of the middle electrode 138M.

Finally in step 85 of FIG. 9B, M1 metallization element 146A is formed above the leftmost of the vias 145T, M1 metallization element 148 is formed above the long via 147L, and M1 metallization element 146B is formed above the short via 147S and the rightmost one of the tall vias 145T.

Step 86 ends the process shown by FIG. 9B.

In accordance with this invention a MIM capacitor is formed as part of a CMOS integration circuit device including the a FET gate layer (i.e. a metal, polysilicon or polysilicon/silicide structure) and a HiK dielectric layer to make a plate of the MIM capacitor.

Advantages of the invention are as follows:

-   -   (a) Provides a capacitor compatible with metal/HiK gate CMOS         integration.     -   (b) The MIM capacitor has better linearity compared to the         current MOS capacitors and hence comprises a better RF device.     -   (c) The use of HiK dielectric material provides high capacitance         density and is suitable for both decoupling and RF capacitors.     -   (d) There is no need for BEOL MIM integration, which is         increasingly difficult with each new generation because of via         height reduction.

While this invention has been described in terms of the above specific embodiment(s), those skilled in the art will recognize that the invention can be practiced with modifications within the spirit and scope of the appended claims, i.e. that changes can be made in form and detail, without departing from the spirit and scope of the invention. Accordingly all such changes come within the purview of the present invention and the invention encompasses the subject matter of the following claims. 

1. A Metal Insulator-Metal (MIM) capacitor formed on a semiconductor substrate comprising: a base comprising a semiconductor substrate having a top surface; a lower capacitor plate selected from the group consisting of: a silicide layer formed on a polysilicon layer formed on said top surface on an isolation region formed in said semiconductor substrate; a doped region formed in said top surface of said semiconductor substrate, with said doped region having an upper exterior surface coplanar with said semiconductor substrate; and a doped region formed in said top surface of said semiconductor substrate, with said doped region having a silicide region formed therein with an upper exterior surface coplanar with said semiconductor substrate; a capacitor High K (HiK) dielectric layer formed on said MIM capacitor lower plate, with said HiK dielectric layer consisting of a material selected from the group consisting of Ta₂O₅, BaTiO₃, HfO₂, ZrO₂, and Al₂O₃; a second capacitor plate formed on said capacitor HiK dielectric layer above said lower capacitor plate with said capacitor HiK dielectric layer and said second capacitor plate being narrower than said lower capacitor plate thereby leaving a surface of said lower capacitor plate exposed; said second capacitor plate being covered by either an etch stop layer alone or the combination of a second HiK dielectric layer, a third capacitor plate and an etch stop layer; a first set of vias extending through said etch stop layer formed in contact with said second capacitor plate; and a second set of vias formed in contact with said MIM lower capacitor plate aside from said capacitor HiK dielectric layer and said second capacitor plate.
 2. The MIM capacitor of claim 1 wherein: said lower capacitor plate is formed in said surface of said substrate in a doped well region; said capacitor HiK dielectric layer is formed on said doped well; said second capacitor plate is formed on said capacitor HiK dielectric layer above said lower capacitor plate in said doped well; and said etch stop layer is formed over said second capacitor plate.
 3. The MIM capacitor of claim 2 wherein: said lower capacitor plate includes said doped well region; said HiK dielectric layer is formed on said top surface of said substrate on said doped well region; said second capacitor plate is formed on said HiK dielectric layer over said lower capacitor plate; said second capacitor HiK dielectric layer is formed on said second capacitor plate, a MIM capacitor top plate is formed on said second capacitor HiK dielectric layer over said second MIM capacitor plate; and said lower capacitor plate is electrically connected to said MIM capacitor top plate; whereby a dual MIM-metal/HiK gate integration is provided over a region of diffused dopant in said doped well region of said substrate.
 4. The MIM capacitor of claim 1 wherein: said isolation region comprises a shallow trench isolation region; said lower capacitor plate includes a silicide layer formed in said top surface of said substrate in said doped well; said capacitor HiK dielectric layer is formed on said top surface of said silicide layer in said doped well; and said second capacitor plate is formed on said capacitor HiK dielectric layer above said lower capacitor plate including said silicide layer in said doped well.
 5. The MIM capacitor of claim 1 wherein: said doped region comprises a doped well, said lower capacitor plate includes said doped well; said capacitor HiK dielectric layer is formed on top of said doped well; said second capacitor plate comprises laminated layers including a doped polysilicon layer which is formed on said capacitor HiK dielectric layer and a silicide layer which is formed on said doped polysilicon layer; silicide contacts formed on said doped well aside from said HiK dielectric layer and said second capacitor plate; a second capacitor HiK dielectric layer is formed on said silicide layer of said second capacitor plate; and a MIM capacitor top plate is formed on said second capacitor HiK dielectric layer over said second capacitor plate including said silicide layer and said doped polysilicon layer; and said lower capacitor plate being electrically connected to said MIM capacitor top plate; whereby a dual MIM with HiK integration is formed with a silicided polysilicon layer sandwiched between said MIM capacitor top plate and said doped well in said substrate.
 6. The MIM capacitor of claim 1 wherein: said lower capacitor plate includes a silicide layer formed in said doped well in said top surface of said substrate; said capacitor HiK dielectric layer is formed on top of said doped well including said silicide layer of said lower capacitor plate; said second capacitor plate comprises an electrode layer formed on said capacitor HiK dielectric layer; a second capacitor HiK dielectric layer is formed on said silicide layer of said capacitor second plate; and a MIM capacitor top plate is formed on said second capacitor HiK dielectric layer above said metal electrode; and said lower capacitor plate being electrically connected to said MIM capacitor top plate; whereby a dual MIM with dual HiK integration is provided over a silicide layer.
 7. The MIM capacitor of claim 1 wherein said lower capacitor plate comprises a doped well formed in said doped region in said top surface of said semiconductor substrate in which a silicide layer has been formed.
 8. The MIM capacitor of claim 1 wherein: said capacitor comprises a dual capacitor with said lower capacitor plate comprising a doped well in said doped region; with said second capacitor plate and a top plate formed thereabove sandwiched with dual HiK layers; and with said lower MIM capacitor plate electrically interconnected to said upper electrode.
 9. The MIM capacitor of claim 8 wherein said second capacitor plate comprises a laminated layer of polysilicon and a silicide layer.
 10. The MIM capacitor of claim 1 wherein: said lower capacitor plate on said STI region comprises a polysilicon layer on which a silicide layer is formed; with said second capacitor plate and a top plate formed above said lower capacitor plate, being sandwiched with dual HiK layers; and with said lower plate electrically interconnected to said upper electrode.
 11. The MIM capacitor of claim 1 wherein: said lower capacitor plate comprises said doped well formed in said top surface of said semiconductor substrate upon which a stack of said IliK dielectric layer and said MIM capacitor second plate have been formed; with sidewall spacers funned adjacent to sidewalls of said MIM capacitor second plate; and with silicide contacts to said doped well juxtaposed with said sidewall spacers.
 12. A Metal Insulator-Metal (MIM) capacitor formed on a semiconductor substrate comprising: a base comprising a semiconductor substrate having a top surface and including a lower capacitor plate formed in said surface selected from the group consisting of: a silicide layer formed on a polysilicon layer formed on said top surface on an isolation region formed in said semiconductor substrate; a doped region formed in said top surface of said semiconductor substrate, with said doped region having an upper exterior surface coplanar with said semiconductor substrate; and a doped region formed in said top surface of said semiconductor substrate, with said doped region having a silicide region formed therein with an upper exterior surface coplanar with said semiconductor substrate; a capacitor High K (HiK) dielectric layer formed on said lower capacitor plate consisting of a material selected from the group consisting of Ta₂O₅, BaTiO₃, HfO₂, ZrO₂, and Al₂O₃; and a second capacitor plate formed on said HiK dielectric layer above said lower capacitor plate; at least a second High K dielectric layer formed above said second capacitor plate and at least a third capacitor plate formed above said second High K dielectric layer; and said third capacitor plate being narrower than said lower capacitor plate; and vias formed in contact with said lower capacitor plate aside from said capacitor HiK dielectric layer and said second capacitor plate.
 13. The MIM capacitor of claim 12 wherein an etch stop is formed on said third capacitor plate with a via contact extending therethrough.
 14. The MIM capacitor of claim 13 wherein: sidewall spacers are formed on sidewalls of said MIM capacitor second plate and on sidewalls of said HiK dielectric layer, a silicide layer is formed in said top surface aside from said sidewall spacers, said capacitor HiK dielectric layer and said MIM capacitor lower plate; and at least one via is formed on said top surface of said silicide layer.
 15. The MIM capacitor of claim 12 wherein: sidewall spacers are formed on sidewalls of said MIM capacitor second plate and on sidewalls of said HiK dielectric layer; a silicide layer is formed in said top surface aside from said sidewall spacers, said capacitor HiK dielectric layer and said MIM capacitor lower plate; and at least one via is formed on said top surface of said silicide layer.
 16. A Metal Insulator-Metal (MIM) capacitor formed on a semiconductor substrate comprising: said semiconductor substrate having a top surface and including a doped well in said top surface, with said doped well having exterior surfaces coplanar with said semiconductor substrate forming a MIM capacitor lower plate; and a capacitor High K (HiK) dielectric layer formed on said MIM capacitor lower plate consisting of a material selected from the group consisting of Ta₂O₅, BaTiO₃, HfO₂, ZrO₂, and Al₂O₃; a MIM capacitor second plate formed on said HiK dielectric layer above said MIM capacitor lower plate, and said capacitor HiK dielectric layer and said second capacitor plate being narrower than said lower capacitor plate thereby leaving a surface of said lower capacitor plate exposed; a silicon nitride etch stop layer formed over said MIM capacitor second plate; a blanket dielectric layer covering said device, a first set of vias extending through said blanket dielectric layer and through said silicon nitride etch stop layer into contact with said second capacitor plate; and a second set of vias extending through said blanket dielectric layer into contact with said MIM lower capacitor plate aside from said capacitor HiK dielectric layer and said second capacitor plate.
 17. The MIM capacitor of claim 16 wherein: sidewall spacers are formed on sidewalls of said MIM capacitor second plate and on sidewalls of said HiK dielectric layer; a silicide layer is formed in said top surface aside from said sidewall spacers, said capacitor HiK dielectric layer and said MIM capacitor lower plate; and said second set of vias being in contact with said silicide layer. 